1. Field of the Invention
Example embodiments of the present invention relate generally to a bit line sense amplifier and method thereof, and more particularly to a bit line sense amplifier and method of amplifying voltage.
2. Description of the Related Art
Conventional semiconductor memory devices may operate at relatively low power supply voltages and at higher speeds, which may complicate manufacturing processes of the semiconductor memory devices. However, test conditions during memory tests of conventional semiconductor memory devices may be configured based on older semiconductor memory devices, which may typically operate at higher power supply voltages and lower speeds. The legacy test conditions used in conventional memory tests may create a number of “false-positives” (i.e., non-defective units treated as defective units).
FIG. 1 is a circuit diagram illustrating a conventional dynamic random-access memory (DRAM) device 100.
Referring to FIG. 1, the DRAM device 100 may include pairs of bit lines BL1, BL1B, BL2, BL2B, BL3 and BL3B, word lines WL0 and WL1, memory cells CELL1 through CELL6 and bit line sense amplifiers 1, 2, and 3. While the above-listed elements are illustrated as included within the conventional DRAM device 100, it is understood that additional memory cells and/or bit line sense amplifiers may be included in a real-world implementation of the DRAM 100 of FIG. 1. Generally, as the DRAM device 100 becomes more highly integrated, a distance between the bit lines may become lower. Accordingly, parasitic bridge resistors BR1 to BR4 may be positioned between the bit lines due to the decreased bit line separation.
FIG. 2 is a circuit diagram illustrating another conventional DRAM device 200 including a sense amplifier connected to a pair of bit lines.
Referring to FIG. 2, the DRAM device 200 may include a memory cell CELL1, pre-charge circuits 11 and 12, bit line sense amplifiers 15 and 16 and a data input/output (I/O) circuit 17. The DRAM device 200 may further include a p-type metal-oxide semiconductor (PMOS) transistor 18 for providing a power supply voltage VCCA to the bit line sense amplifier 15, and an n-type metal-oxide semiconductor (NMOS) transistor for providing a ground voltage VSS to the bit line sense amplifier 16.
A conventional process for testing the DRAM 200 will now be described.
Referring to FIG. 2, the pair of bit lines BL1 and BL1B (not shown, e.g., see FIG. 1) may be separated into a pair of array bit lines BL1_A and BL1B_A and a pair of sense bit lines BL1_S and BL1B_S. Isolation control circuits 13 and 14 may electrically connect the pair of array bit lines BL1_A and BL1B_A and the pair of sense bit lines BL1_S and BL1B_S, respectively, in response to isolation control signals ISOL and ISOR.
Referring to FIG. 2, the pair of sense bit lines BL1_S and BL1B_S may be pre-charged by the pre-charge circuits 11 and 12 to a voltage VBL. The voltage VBL may typically be set to half of a memory cell array power supply voltage.
Referring to FIG. 2, if the pre-charge operation is completed and a word line WL is activated such that a transistor in the memory cell CELL1 is turned on, data of the memory cell may be outputted to the pair of array bit lines BL1_A and BL1B_A. If transistors configuring the isolation control circuits 13 and 14 are turned on, signals of the pair of array bit lines BL1_A and BL1B_A may be respectively transferred to the pair of sense bit lines BL1_S and BL1B_S. A cell capacitor may share charge with the bit lines BL1_A and BL1_S. If bit line sensing control signals LANG and LAPG are enabled after the charge is sufficiently shared, signals of the pair of sense bit lines BL1_S and BL1B_S may be amplified by sense amplifiers 15 and 16.
However, in a test mode, the bit line sensing control signals LANG and LAPG may not be enabled until a relatively long period after the pair of sense bit lines BL1_S and BL1B_S is pre-charged and data of the memory cell CELL1 is transferred to the pair of sense bit lines BL1_S and BL1B_S via the charge sharing process. Thus, pre-charge control signals EQR and EQL may be in a disabled state because the pre-charging operation may already have been completed. As described with reference to FIG. 1, a leakage current may flow through the parasitic bridge resistors BR1 to BR4, which may be positioned between adjacent bit lines. Therefore, a voltage level of the pair of sense bit lines BL1_S and BL1B_S may be reduced (e.g., below a voltage threshold) before the bit line sensing control signals LANG and LAPG are enabled after the pair of sense bit lines BL1_S and BL1B_S is pre-charged. Consequently, the reduced voltage level may not be sensed by the sense amplifier.
In the testing operation described above with respect to FIG. 2, non-defective DRAM devices may be treated as defective in the bit line test, and a production yield may thereby be reduced.